Field of the Invention
The present invention relates to integrated circuits and in particular to a method for providing an on-chip variation determination and an integrated circuit utilizing the same.
Description of the Related Art
Electronic design automation (EDA) tools are widely adopted in Integrated Circuit (IC, also referred to as a chip) design and layout for simulating the timing of the circuits and determining cell placement. EDA tools are operated on a computer without the needs of IC fabrication. One such EDA tool can perform Static Timing Analysis (STA), which computes the expected timing of digital circuits on an IC without requiring simulation.
STA is performed with reasonable accurate models of devices and cells under various sets of expected variations, referred to as different “corners”. Process, Voltage, Temperature (PVT) corners are based on assumptions regarding process, operating voltage, and operating temperature variations in device operation from one IC to another. The circuits are required to pass all timing requirements under various PVT conditions in STA before getting a timing signoff and proceeding to be manufactured.
As the semiconductor technology continues scaling down, the impact of on-chip variation deviating from STA becomes significant. Therefore, v a method providing an on-chip variation determination and an integrated circuit utilizing the same are disclosed for an On-chip Variation (OCV) determination, which determine the intrinsic variation of semiconductor processes and their impact on STA.